Embedded MCQ Questions
1. A micro controller at-least should consist
of:
a) RAM, ROM, I/O devices, serial and parallel ports and timers
b) CPU, RAM, I/O devices, serial and parallel ports and timers
c) CPU,RAM, ROM, I/O devices, serial and parallel ports and timers
d) CPU, ROM, I/O devices and timers
a) RAM, ROM, I/O devices, serial and parallel ports and timers
b) CPU, RAM, I/O devices, serial and parallel ports and timers
c) CPU,RAM, ROM, I/O devices, serial and parallel ports and timers
d) CPU, ROM, I/O devices and timers
2.
Unlike micro processors, micro controllers
make use of batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
3.
What is the order decided by a processor or the CPU of a
controller to execute an instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
4.
How are
micro controllers classified on the basic of internal bus width?
a) 8,16,32,64 bits
b) 4,8,16,32 bits
c) 8,16 bits
d) 4,16,32 bits
a) 8,16,32,64 bits
b) 4,8,16,32 bits
c) 8,16 bits
d) 4,16,32 bits
5.
How is the
performance and the computer capability affected by increasing its internal bus
width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width don’t affect the performance in any way
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width don’t affect the performance in any way
6.
Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
7.
Give the
names of the buses present in a controller for transferring data from one place
to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
8.
What is the
file extension that is loaded in a micro controller for executing any
instruction?
a) .doc
b) .c
c) .txt
d) .hex
a) .doc
b) .c
c) .txt
d) .hex
9.
What are the
most appropriate criterion for choosing the right micro controller of our
choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
a) speed
b) availability
c) ease with the product
d) all of the mentioned
10.
Why micro
controllers are not called general purpose devices?
a) because they are based on VLSI technology
b) because they are not meant to do a single work at a time
c) because they are cheap
d) because they consume low power
a) because they are based on VLSI technology
b) because they are not meant to do a single work at a time
c) because they are cheap
d) because they consume low power
11.
How many
types of architectures are available, for designing a device that is able to
work on its own?
a) 3
b) 2
c) 1
d) 4
a) 3
b) 2
c) 1
d) 4
12.
Which
architecture is followed by general purpose microprocessors?
a) Harvard architecture
b) Von Neumann architecture
c) none of the mentioned
d) all of the mentioned
a) Harvard architecture
b) Von Neumann architecture
c) none of the mentioned
d) all of the mentioned
13.
Which architecture involves both the volatile and the non
volatile memory?
a) Harvard architecture
b) Von Neumann architecture
c) none of the mentioned
d) all of the mentioned
a) Harvard architecture
b) Von Neumann architecture
c) none of the mentioned
d) all of the mentioned
14.
Which
architecture provides separate buses for program and data memory?
a) Harvard architecture
b) Von Neumann architecture
c) none of the mentioned
d) all of the mentioned
a) Harvard architecture
b) Von Neumann architecture
c) none of the mentioned
d) all of the mentioned
15.
Which micro
controller don’t match with its architecture below?
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
16.
Harvard architecture allows:
a) separate program and data memory
b) pipe-ling
c) complex architecture
d) all of the mentioned
a) separate program and data memory
b) pipe-ling
c) complex architecture
d) all of the mentioned
17.
Which out of
the following supports Harvard architecture?
a) ARM7
b) Pentium
c) SHARC
d) all of the mentioned
a) ARM7
b) Pentium
c) SHARC
d) all of the mentioned
18.
Why most of the DSPs use Harvard architecture?
a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) none of the mentioned
d) both of the mentioned
a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) none of the mentioned
d) both of the mentioned
19.
Which of the
following supports CISC as well as Harvard architecture?
a) ARM7
b) ARM9
c) SHARC
d) none of the mentioned
a) ARM7
b) ARM9
c) SHARC
d) none of the mentioned
20.
n Neumann
c) none of the mentioned
d) both of the mentioned
c) none of the mentioned
d) both of the mentioned
21.
. 8051
series of micro controllers are made by which of the following companies?
a) Atmel
b) Philips
c) none of the mentioned
d) both of the mentioned
a) Atmel
b) Philips
c) none of the mentioned
d) both of the mentioned
22.
AT89C2051
has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
23.
8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
a) 2
b) 3
c) 1
d) 0
24.
When 8051
wakes up then 0x00 is loaded to which register?
a) DPTR
b) SP
c) PC
d) PSW
a) DPTR
b) SP
c) PC
d) PSW
25.
When the micro controller executes some arithmetic
operations, then the flag bits of which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
a) PSW
b) SP
c) DPTR
d) PC
26.
How is the
status of the carry, auxiliary carry and parity flag affected if write
instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
27.
How are the bits of the register PSW affected if we select
Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
28.
If we push
data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) none of the mentioned
d) both of the mentioned
a) increases with every push
b) decreases with every push
c) none of the mentioned
d) both of the mentioned
29.
On power up,
the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
30.
How many
bytes of bit addressable memory is present in 8051 based micro controllers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
31.
DJNZ
R0,label is how many bit instruction?
a) 2
b) 3
c) 1
d) Cant be determined
a) 2
b) 3
c) 1
d) Cant be determined
32.
JZ, JNZ,
DJNZ, JC, JNC instructions monitor the bits of which register ?
a) DPTR
b) B
c) A
d) PSW
a) DPTR
b) B
c) A
d) PSW
33. Calculate the jump code for again and
here if code starts at 0000H
34.
MOV R1,#0
35.
MOV A,#0
36.
MOV R0,#25H
37.
AGAIN:ADD A,#0ECH
38.
JNC HERE
39.
HERE: INC R1
40.
DJNZ R0,AGAIN
41.
MOV R0,A
42.
END
43. a)F3,02
b)F9,01
c)E9,01
d)E3,02
b)F9,01
c)E9,01
d)E3,02
44.
When the
call instruction is executed the top most element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
45.
LCALL
instruction takes
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
46.
Are PUSH and
POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
a) yes
b) no
c) none of the mentioned
d) cant be determined
47.
What is the
time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
48. Find
the number of times the following loop will be executed
MOV R6,#200
BACK:MOV R5,#100
HERE:DJNZ R5, HERE
DJNZ R6,BACK
END
a)100
b)200
c)20000
d)200000
b)200
c)20000
d)200000
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